Conformal has two command modes named vpxmode and tclmode
Depending on what mode is used the command semantics changes
E.g.:
VPXMODE : read design ...
TCLMODE : read_design ...
Conformal run has two system modes named "setup" and "lec"
To switch between them use the command "set system mode <mode_name>"
SETUP
Read source code
Set compile strategy like naming style, naming rules etc
Manage black boxes
Manage mapped points
Manage Constraints
LEC
Manage compare points and parameters
Set compile strategy
Diagnose
Reporting
read design $PATH/*.sv -SystemVerilog -Golden
The "UNDEFINED CELL" command is used to deal with modules/cells which are not present in the run i.e. files missing.
The run can convert them to black box or error out based on the option given. Run this before read_design
E.g.:
set undefined cell black_box
If there is a difference in the module names of your GOLDEN and REVISED database, renaming rules are applied to map them.
E.g.:
add renaming rule <name_this_rule> "NAME_IN_THE_DB" "RENAME_TO_THIS" "GOLDEN/REVISED" "-module/-instance"
add renaming rule rename_rule_1 arbiter_mod generic_arbiter -Golden -module
In LEC mode compare command performs the GOLDEN vs REVISED comparison. Here is a couple of useful options for compare
E.g.:
set system mode lec
set compare effort high
add compare points -all
compare
List all non-equivalent
diagnose -noneq > filename
Other Useful reports
report statistics
report renaming rule
report mapped points
report unmapped points
report floating signals -Undriven -Both -Net -All
report tied signals
All these report commands output on STDOUT and needs to be manually redirected
Along with vpxmode, conformal also supports tclmode
E.g.:
tclmode
set_system_mode setup
# Get current run status
set runStatus [get_exit_code]
# Loading procs
source <some_proc_source.tcl>
# Calling proc
set procStatus [procName]
exit <Exit code>
1. Black boxes will be added as a single mapped and compared points
2. If black box have different port list in G and R, manual mapping is needed
3. If "undefined cell" is set to black box, make sure SV ".*" notation is not used in the module instantiating the black box
4. Key points are
PI
PO
DFF
D-Latch
TIE-E Gates (error gate from x-assignment exists in revised design)
TIE-Z (high impedance or floating signal)
BBOX
Cut gates (artificial gates that break combo loop)
5. Mapping
■ Extra unmapped points are key points that are present in only one of the designs, Golden or Revised.
■ Unreachable unmapped points are key points that do not have an observable point, such as a primary output.
■ Not-mapped unmapped key points are key points that are reachable but do not have a corresponding point in the logic fan-in cone of the corresponding design.