The SV macro extension provides a way to interpolate arguments or variables, a token delimiter and a escape character as extension to verilog macros
Variable interpolation `" :
1. No interpolation case
`define NO_INTERPOLATION(VAR) "This is VAR"
e.g.:
`NO_INTERPOLATION(WAR) ---> This is VAR
2. Interpolation case
`define INTERPOLATION(VAR) `"This is VAR`"
e.g.:
`INTERPOLATION(WAR) ---> This is WAR
This is similar to using single quote vs double quote in most shell programs
Token delimiter `` :
1. No delimiter case
`define NO_DELIMITER(VAR) `"This_is_VAR_`"
e.g.:
`NO_DELIMITER(WAR) --> This_is_VAR_
The variable/argument VAR is not interpolated due to no proper word boundary
around the variable/argument/token
2. Delimiter case
`define DELIMITER(VAR) `"This_is_``VAR``_`"
e.g.:
`DELIMITER(WAR) --> This_is_WAR_
The `` should be used around the token/argument/variable is there is word boundary
It is similar to adding flower braces in bash script i.e. "This_is_${VAR}_text"
Escape character `\`" :
This just provides a escape character.
1. Without escape char
`define ESC_DEMO(ARG) `"Hi ``ARG How are you?`"
e.g.:
`ESC_DEMO(VINAY) --> Hi VINAY How are you?
2. With escape char
`define ESC_DEMO(ARG) `"Hi `\`"``ARG`\`" How are you?`"
e.g.:
`ESC_DEMO(VINAY) --> Hi "VINAY" How are you?