Create_clock
This constraint is used to specify the behavior and characteristics of a clock. The characteristics are,
1. Period
2. Active edge
3. Duty cycle
Syntax:
create_clock -period period_value # Period of the clock
[source_objects] # The physical port/pin/net on the design. If missing this clock is virtual
[-name clock_name] # Assign a logical name for further use.
[-waveform edge_list] # Waveform spec of the clock.If missing, clock is assumed 50% duty cycle.
[-add] # To add multiple specification
[-comment comment_string] # Comment
Examples:
1. Create a clock with uneven duty cycle.
create_clock -period 10 -name CLOCK -waveform {3 5 8 9} [get_ports clk_i]
_____ __ _____ __ _____ __
_________| |________| |____________| |________| |____________| |________| |___
0 1 2 3 4 5 6 7 8 9 10 13 15 18 19 20 23 25 28 29
2. Two spec on the same clock. This can happen if the clock is driven from outside the boundary through a clock mux.
create_clock -name C1 -period 10 [get_ports clk_i]
create_clock -name C2 -period 15 [get_ports clk_i] -add
create_generated_clocks
Generated clocks are the signals which are derived from another clock source. Clock generation can be done in multiple ways,
1. Clock divider
2. Clock multipliers
3. Clock gating
Syntax:
create_generated_clock [source_objects] # Object where clock is generated
-source clock_source_pin # Physical Port/Pin/Net (Master clock pin)
[-master_clock master_clock_name] # Clock to use if multiple clock fan-in to master pin
[-name generated_clock_name] # Logical name for generated clock
[-edges edge_list] # Edge list with reference to master clock* (not time units)
[-divide_by factor] # Divide factor
[-multiply_by factor] # Multiply factor
[-invert] # Invert the spec, essentially a not gate
[-edge_shift shift_list] # Move edges in time units* (No. of args == -edges)
[-duty_cycle percent] # Duty cycle of generated clocks
[-combinational] # Clock is sent as output. Can only be -divide_by 1
[-add] # To add multiple spec
[-comment comment_string] # Comment
Examples:
1. Generated clock with division factor 3. The source clocks is driven from outside a boundary through clock mux.
create_clock -name C1 -period 10 [get_ports CLK]
create_clock -name C2-period 15 [get_ports CLK] -add
# The following generated clock is based on C1’s characteristics
create_generated_clock -name GC1 -divide_by 3 -source [get_port CLK] -master_clock C1 [get_pins FF2/Q]
# The following generated clock is based on C2’s characteristics
create_generated_clock -name GC2 -divide_by 3 -source [get_port CLK] -master_clock C2 [get_pins FF2/Q] -add
2. Clock sent out as output for source synchronous interface
create_generated_clock -name CLKOUT -combinational -source [get_pins FF1/Q] [get_ports CLKOUT]
Generated clock gotchas:
1. If you define a generated clock make sure it is actually generated by the specified source object. Conversely, if a flip-flip or register is driven by a clock which is in fanout of another clock, make sure there is create_generated_clock constraint set on it. A missing generated clock may result in unconstrained registers.
2. When multiple clocks converge on the source pin of a clock, make sure to specify the master clock with the generated clock definition.
3. If you are specifying more than one generated clock constraint on a pin because of multiple sources, make sure to use the -add option; otherwise, the last specified constraint would override.
4. Avoid clock convergence via multiple combinational paths as it can result in a pulse. If clocks converge via multiple paths (combinational and sequential), then it is important to disable the sequential path
set_clock_uncertainty -setup VAL CLOCK
set_clock_uncertainty -hold VAL CLOCK
set_clock_transition -min/max -rise/fall VAL CLOCK
# Alternative to clock_transition, set_driving_cell can be provided.
set_clock_latency VAL -min/max CLOCK
set_clock_latency -source VAL -min/max CLOCK
Clock group provides the relationship between different clocks.
set_clock_group -asynchronous -group {CLKA CLKB} -group {CLKC CLKD}
In the above example, CLKA and CLKB are synchronous and are asynchronous to CLKC and CLKD (which are sync to each other)
set_clock_group -asynchronous -group {CLKA}
Here CLKA is async to all other clocks.
Apart from "-asynchronous", there are other optons available
-physically_exclusive
-logically_exclusive
**check solvnet
set_input_delay
# assume that T_C2Q + TComb = 10ns
set_input_delay -clock CLOCK -max 10 [get_ports D}
# assume that TComb +T_setup = 2ns
set_output_delay -clock CLOCK -max 2 [get_ports D}
Feed through paths are those where the input to output path has no flops but only comb paths.
Designer need to set set_max_delay & set_min_delay constraints on these paths.
The IO ports are to be constrainted depending on the type of signal being driven.
For sync signals use "set_input_delay" and "set_output_delay"
For async signals, can use "set_max_delay"
SET_INPUT_DELAY
EXTERNAL BOUNDARY MODULE
FLOP --------- D1 ----------> | >--------D2-------FLOP
Here set input delay is used to specify "D1". So the timing analysis will check to make sure D1 + D2 + Tsu(FLOP) meets (less than) the Tclock.
SET_OUTPUT_DELAY
EXTERNAL BOUNDARY MODULE
FLOP --------- D1 ---------- <| <--------D2-------FLOP
Here set output delay is used to specify "D1". So the timing analysis will check to make sure Tc2q + D1 + D2 meets the Tclock
SET_MAX_DELAY/SET_MIN_DELAY
PORT/PIN --------------- COMBO -------------------- PORT/PIN
Used for feed through paths or async IO paths.
status set_max_delay
delay_value
[-rise | -fall]
[-from from_list
| -rise_from rise_from_list
| -fall_from fall_from_list]
[-through through_list]
[-rise_through rise_through_list]
[-fall_through fall_through_list]
[-to to_list
| -rise_to rise_to_list
| -fall_to fall_to_list]
[-group_path group_name]
[-reset_path]
[-comment comment_string]
[-ignore_clock_latency]
-fall_from CLOCK_OBJECT --> All flops sampled from negedge of this clock are picked up. If clock is inverted, the all rise edge flops using the inverted clock are also picked up.
-rise_from CLOCK_OBJECT --> All flops sampled on rise edge of this clock are picked up. If clock is inverted, the all fall edge flops using the inverted clock are also picked up.
# create collection
set iport [all_inputs]
# create list
set clockList [list clk1 clk2 clk3]
# Removed clocks from input collection
set nonClockList [remove_from_collection $iport $clockList]
# Filter ports using name attribute
set attr_name "name"
set clockListAlternate [filter_collection $iport "$attr_name=~clk*"]
# Outputs
set_load [load_of[get_lib_pins LIB_NAME/BUF_CELL/INP]] [all_outputs]
# Inputs - analogous to having a cell drving the input
set_driving_cell -lib_cell BUF_CELL -min/max -input_transition_rise/input_transition_fall [get_attribute [get_lib_pins LIB_NAME/BUF_CELL/INP] max_transition] [all_inputs]
# Picking up attributes
get_attribute [get_lib_pins LIB_NAME/BUF_CELL/INP] max_transition
In this command, the attribute name depends on what is written in the lib file.
MCP is a way to change the default setup and hold edges (launch and capture).
For majoirty of the design, with a MCP setup of N, the hold MCP is N-1 is used.
set_multicycle_path 2 -setup -from MOD/CLK
set_multicycle_path 1 -hold -from MOD/CLK
# Fast to slow clock case
# Moving the default start edge
# The following command moves the start edge by 2 for setup and
# moves default hold edge back by 2
s1 __ s2 __ s3 __ s4 __ __ __
__| |__| |__| |__| |__| |__| |__
___________ ___________
__| |___________|
# setup check is most pessimistic from S4 (which is also done by tool).
# The MCP with -start should be applied to hold to move it back to S1
set_multicycle_path 3 -setup -from MOD1/Q -to MOD2/D -start
set_multicycle_path 2 -hold -from MOD1/Q -to MOD2/D -start
# Slow to fast clock case
# Need to move the default capture edge
# The following constraint moves the capture edge i.e. endpoint by 4
___________ ___________
__| |___________|
s1 __ s2 __ s3 __ s4 __ s5 __ __
__| |__| |__| |__| |__| |__| |__
# Since timing can be relaxed to capture at S5, we move the endpoint for setup by 4
# For hold, we need to move it back from S4 (Default due to setup being check at S5)
# to S1. So MCP of 3 with -end is needed.
set_multicycle_path 4 -setup -from MOD1/Q -to MOD2/D -end
set_multicycle_path 3 -hold -from MOD1/Q -to MOD2/D -end